1. Field of the Invention
This invention relates to computer memory and bandwidth utilization associated with the memory.
2. Description of the Related Art
One typical goal of main memory compression schemes is to reduce the bandwidth requirements of off-chip accesses to main memory. In any such scheme, the memory controller needs to know for a given data request whether it must read the full size of the block, or a reduced size if the block is compressed.
There are a variety of memory compression approaches. Many schemes use potentially large on-chip data structures to store (or cache) the “compressed or not compressed” state of various main memory blocks. These on-chip structures are queried before a main memory access to determine whether the full or reduced memory request size should be used. This requires large on-chip structures if a large amount of memory is to be compressible.
Another solution is to encode the compressed/uncompressed state of a block in the main memory itself along with the data in question. For example, either an additional data bit may be provided to encode the state, or the data may be tagged by inverting the ECC bits. First the data is accessed assuming it is compressed, and if the data returned indicates that it is not compressed, the remainder of the data is accessed. This approach results in poor latency for access to uncompressed data, as it requires a memory request to wait for the first (presumed compressed) data to return before issuing a second request.